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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC950/951 are 3.3V compatible, PLL based clock driver devices targeted for high performance clock tree designs. With output frequencies of up to 180MHz and output skews of 375ps the MPC950 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle-to-cycle and long term jitter. This parameter is of significant importance when the clock driver is providing the reference clock for PLL's on board today's microprocessors and ASiC's. The devices offer 9 low skew outputs, the outputs are configurable to support the clocking needs of the various high performance microprocessors.
MPC950 MPC951
LOW VOLTAGE PLL CLOCK DRIVER
* Fully Integrated PLL * Oscillator or Crystal Reference Input * Output Frequency up to 180MHz * Outputs Disable in High Impedance * Compatible with PowerPCTM, Intel and High Performance RISC
Microprocessors
* TQFP Packaging * Output Frequency Configurable * 100ps Typical Cycle-to-Cycle Jitter
FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-02
Two selectable feedback division ratios are available on the MPC950 to provide input reference clock flexibility. The FBSEL pin will choose between a divide by 8 or a divide by 16 of the VCO frequency to be compared with the input reference to the MPC950. The internal VCO is running at either 2x or 4x the high speed output, depending on configuration, so that the input reference will be either one half, one fourth or one eighth the high speed output. The MPC951 replaces the crystal oscillator and internal feedback of the MPC950 with a differential PECL reference input and an external feedback input. These features allow for the MPC951 to be used as a zero delay, low skew fanout buffer. In addition, the external feedback allows for a wider variety of input-to-output frequency relationships. The MPC951 REF_SEL pin allows for the selection of an alternate LVCMOS input clock to be used as a test clock or to provide the reference for the PLL from an LVCMOS source. The MPC950 provides an external test clock input for scan clock distribution or system diagnostics. In addition the REF_SEL pin allows the user to select between a crystal input to an on-board oscillator for the reference or to chose a TTL level oscillator input directly. The on-board crystal oscillator requires no external components beyond a series resonant crystal. Both the MPC950 and MPC951 are fully 3.3V compatible and require no external loop filter components. All inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50 transmission lines. Select inputs do not have internal pull-up/pull-down resistors and thus must be set externally. If the PECL_CLK inputs are not used, they can be left open. For series terminated 50 lines, each of the MPC950/951 outputs can drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm 32-lead TQFP package to provide the optimum combination of board density and performance.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
2/97
(c) Motorola, Inc. 1997
1
REV 4
MPC950 MPC951
MPC950 LOGIC DIAGRAM
fsela PLL_En Tclk Ref_Sel
xtal1 xtal2
xtal OSC
PHASE DETECTOR
VCO 200-480MHz
/2//4
Qa
LPF /8//16 FBsel fselb
(Pull Down)
/4//8
Qb
/4//8
Qc0 Qc1
fselc MR/OE POWER-ON RESET /4//8 Qd0 Qd1 fseld Qd2 Qd3 Qd4
GNDO
GNDO
VCCO
VCCO
Qd0
Qd1
Qc0
Qc1
FUNCTION TABLES
Ref_Sel Function TCLK XTAL_OSC Function PLL Enabled PLL Bypass Function /8 /16 Function Outputs Disabled Outputs Enabled Function Qa = /4; Qb:d = /8 Qa = /2; Qb:d = /4
24 GNDO Qb VCCO Qa GNDO TCLK PLL_En Ref_Sel 25 26 27 28
23
22
21
20
19
18
17 16 15 14 13 Qd2 VCCO Qd3 GNDO
1 0 PLL_En 1 0 FBsel
MPC950
29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9 Qd4 VCCO MR/OE xtal2
1 0 MR/OE 1 0 fseln 1 0
VCCA
GNDI
fsela
fselb
fseld
MOTOROLA
FBsel
xtal1
fselc
2
TIMING SOLUTIONS BR1333 -- Rev 6
MPC950 MPC951
MPC951 LOGIC DIAGRAM
fsela PLL_En Tclk Ref_Sel
PECL_CLK PECL_CLK
(Pull Up)
PHASE DETECTOR
VCO 200-550MHz
/2//4
Qa
LPF Ext_FB fselb
(Pull Down)
/4//8
Qb
/4//8
Qc0 Qc1
fselc MR/OE POWER-ON RESET /4//8 Qd0 Qd1 fseld Qd2 Qd3 Qd4
GNDO
GNDO
VCCO
VCCO
Qd0
Qd1
Qc0
Qc1
FUNCTION TABLES
24 GNDO Qb VCCO Qa GNDO TCLK PLL_En Ref_Sel 25 26 27 28 23 22 21 20 19 18 17 16 15 14 13 Qd2 VCCO Qd3 GNDO Qd4 VCCO MR/OE PECL_CLK Ref_Sel 1 0 PLL_En 1 0 MR/OE 1 0 fseln 1 0 PECL_CLK VCCA Ext_FB GNDI fsela fselb fseld fselc Function TCLK PECL_CLK Function PLL Enabled PLL Bypass Function Outputs Disabled Outputs Enabled Function Qa = /4; Qb:d = /8 Qa = /2; Qb:d = /4
MPC951
29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9
TIMING SOLUTIONS BR1333 -- Rev 6
3
MOTOROLA
MPC950 MPC951
FUNCTION TABLE - MPC950/951
INPUTS fsela fselb fselc fseld Qa(1) 2x 2x 2x 2x 2x 2x 2x 2x x x x x x x x x OUTPUTS Qb(1) x x x x x/2 x/2 x/2 x/2 x x x x x/2 x/2 x/2 x/2 Qc(2) x x x/2 x/2 x x x/2 x/2 x x x/2 x/2 x x x/2 x/2 Qd(5) x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 x x/2 Total 2x 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TOTALS Total x 8 3 6 1 7 2 3 0 9 4 7 2 8 3 6 1 Total x/2 0 5 2 7 1 6 5 8 0 5 2 7 1 6 3 8
0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 NOTE: x = fVCO/4; 200MHz < fVCO < 480MHz.
ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 4.6 VDD + 0.3 20 125 Unit V V mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
DC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Maximum Quiescent Supply Current 25 90 115 LVCMOS Inputs LVCMOS Inputs PECL_CLK PECL_CLK 300 VCC-2.0 2.4 0.5 120 4 Min 2.0 Typ Max 3.6 0.8 1000 VCC-0.6 Unit V V mV mV V V A pF pF mA Per Output All VCC Pins Note 1. IOH = -40mA, Note 2. IOL = 40mA, Note 2. Condition
ICCPLL Maximum PLL Supply Current 15 20 mA VCCA Pin Only 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "HIGH" input is within the VCMR range and the input swing lies within the VPP specification. 2. The MPC950/951 outputs can drive series or parallel terminated 50 (or 50 to VCC/2) transmission lines on the incident edge (see Applications Info section).
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TIMING SOLUTIONS BR1333 -- Rev 6
MPC950 MPC951
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70C)
Symbol tr, tf fref fXtal frefDC Characteristic TCLK Input Rise/Falls Reference Input Frequency Crystal Oscillator Frequency Reference Input Duty Cycle Note 1. 10 25 Min Max 3.0 Note 1. 25 75 Unit ns MHz MHz % Note 2. Condition
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs. 2. See Applications Info section for more crystal information.
AC CHARACTERISTICS (TA = 0C to 70C, VCC = 3.3V 5%)
Symbol tr, tf tpw tsk(O) Characteristic Output Rise/Fall Time Output Duty Cycle Output-to-Output Skews Same Frequencies Different Frequencies Qafmax < 150MHz Qafmax > 150MHz fVCO PLL VCO Lock Range Maximum Output Frequency Input to Ext_FB Delay (Note 1.) Output Disable Time Output Enable Time Cycle-to-Cycle Jitter (Peak-to-Peak) Maximum PLL Lock Time 100 10 Feedback = VCO/4 Feedback = VCO/8 Feedback = VCO/16 Qa (/2) Qa/Qb (/4) Qb (/8) TCLK PECL_CLK 50 -950 250 -770 200 200 200 Min 0.10 tCYCLE/2-1000 200 325 Typ Max 1.0 tCYCLE/2+1000 375 500 750 480 480 480 180 120 60 400 -600 7 6 MHz MPC951 MPC950 or 951 MPC950 Unit ns ps ps Condition 0.8 to 2.0V
fmax
MHz
tpd tPLZ,HZ tPZL tjitter tlock
ps ns ns ps ms
fref = 50MHz Feedback=VCO/8
Note 2.
1. The specification is guaranteed for the MPC951 only. The tpd window is specified for a 50Mhz input reference clock. The window will enlarge/reduce proportionally from the minimum limits with an increase/decrease of the input reference clock period. 2. See Applications Info section for more jitter information.
APPLICATIONS INFORMATION
Programming the MPC950/951 The MPC950/951 clock driver outputs can be configured into several frequency relationships, in addition the external feedback option of the MPC951 allows for a great deal of flexibility in establishing unique input to output frequency relationships. The output dividers for the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers ensures that the output duty cycle is always 50%. Table 1 illustrates the various output configurations, the table describes the outputs using the VCO frequency as a reference. As an example for a 4:2:1 relationship the Qa outputs would be set at VCO/2, the Qb's and Qc's at VCO/4 and the Qd's at VCO/8. These settings will provide output frequencies with a 4:2:1 relationship. The division settings establish the output relationship, but one must still ensure that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL is such that for output frequencies between 25 and 180MHz the MPC950/951 can generally be configured into a stable region. The relationship between the input reference and the output frequency is also very flexible. Table 2 shows the multiplication factors between the inputs and outputs for the MPC950. For external feedback (MPC951) Table 1 can be used to determine the multiplication factor, there are too many potential combinations to tabularize the external feedback condition. Figure 1 through Figure 6 illustrates several programming possibilities, although not exhaustive it is representative of the potential applications.
TIMING SOLUTIONS BR1333 -- Rev 6
5
MOTOROLA
MPC950 MPC951
Using the MPC951 as a Zero Delay Buffer The external feedback option of the MPC951 clock driver allows for its use as a zero delay buffer. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The input reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When used as a zero delay buffer the MPC951 will likely be in a nested clock tree application. For these applications the MPC951 offers a LVPECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The MPC951 then can lock onto the LVPECL Table 1. Programmable Output Frequency Relationships
INPUTS fsela 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 fselb 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 fselc 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 fseld 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Qa VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 Qb VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 OUTPUTS Qc VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 Qd VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8
reference and translate with near zero delay to low skew LVCMOS outputs. Clock trees implemented in this fashion will show significantly tighter skews than trees developed from CMOS fanout buffers. To minimize part-to-part skew the external feedback option again should be used. The PLL in the MPC951 decouples the delay of the device from the propagation delay variations of the internal gates. From the specification table one sees a Tpd variation of only 200ps, thus for multiple devices under identical configurations the part-to-part skew will be around 1000ps (350ps for Tpd variation plus 350ps output-to-output skew plus 300ps for I/O jitter). By running the devices at the highest possible input reference, this part-to- part skew can be minimized. Higher input reference frequencies will minimize both I/O jitter and tpd variations.
Table 2. Input Reference versus Output Frequency Relationships (MPC950 Only)
FB_Sel = `1' Config 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 fsela 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 fselb 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 fselc 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 fseld 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Qa 4x 4x 4x 4x 4x 4x 4x 4x 2x 2x 2x 2x 2x 2x 2x 2x Qb 2x 2x 2x 2x x x x x 2x 2x 2x 2x x x x x Qc 2x 2x x x 2x 2x x x 2x 2x x x 2x 2x x x Qd 2x x 2x x 2x x 2x x 2x x 2x x 2x x 2x x Qa 8x 8x 8x 8x 8x 8x 8x 8x 4x 4x 4x 4x 4x 4x 4x 4x FB_Sel = `0' Qb 4x 4x 4x 4x 2x 2x 2x 2x 4x 4x 4x 4x 2x 2x 2x 2x Qc 4x 4x 2x 2x 4x 4x 2x 2x 4x 4x 2x 2x 4x 4x 2x 2x Qd 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x
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TIMING SOLUTIONS BR1333 -- Rev 6
MPC950 MPC951
MPC950 `1' `1' `1' `0' `0' 16.66MHz fsela fselb fselc fseld FBsel Input Ref Qa Qb Qc Qd 1 1 2 5 66.66MHz 33.33MHz 33.33MHz 66.66MHz 33.33MHz Input Ref `1' `0' `0' `1' `1' fsela fselb fselc fseld FBsel
MPC950 Qa Qb Qc Qd 1 1 2 5 66.66MHz 66.66MHz 66.66MHz 33.33MHz
Figure 1. Dual Frequency Configuration
Figure 2. Dual Frequency Configuration
MPC950 `1' `1' `1' `1' `0' 16.66MHz fsela fselb fselc fseld FBsel Input Ref Qa Qb Qc Qd 1 1 2 5 66.66MHz 33.33MHz 33.33MHz 33.33MHz 20MHz Input Ref `0' `0' `1' `1' `0' fsela fselb fselc fseld FBsel
MPC950 Qa Qb Qc Qd 1 1 2 5 160MHz 80MHz 40MHz 40MHz
Figure 3. Dual Frequency Configuration
Figure 4. Triple Frequency Configuration
MPC951 `1' `0' `0' `0' fsela fselb fselc fseld Qa Qb Qc Ext_FB 75MHz Input Ref Qd
1 1 2 5 1
MPC951 75MHz 75MHz 75MHz 75MHz 25MHz Ext_FB Input Ref `0' `0' `0' `1' fsela fselb fselc fseld Qa Qb Qc Qd
1 1 2 5 1
100MHz 50MHz 50MHz 25MHz
Figure 5. "Zero" Delay Buffer
Figure 6. "Zero" Delay Frequency Multiplier
Jitter Performance of the MPC950/951 With the clock rates of today's digital systems continuing to increase more emphasis is being placed on clock distribution design and management. Among the issues being addressed is system clock jitter and how that affects the overall system timing budget. The MPC950/951 was designed to minimize clock jitter by employing a differential bipolar PLL as well as incorporating numerous power and ground pins in the design. The following few paragraphs will outline the jitter performance of the MPC950/951, illustrate the measurement limitations and provide guidelines to minimize the jitter of the device. The most commonly specified jitter parameter is cycle-to-cycle jitter. Unfortunately with today's high performance measurement equipment there is no way to measure this parameter for jitter performance in the class demonstrated by the MPC950/951. As a result different methods are used which approximate cycle-to-cycle jitter.
The typical method of measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements and record peak-to-peak as well as standard deviations of the jitter. Care must be taken that the measured edge is the edge immediately following the trigger edge. If this is not the case the measurement inaccuracy will add significantly to the measured jitter. The oscilloscope cannot collect adjacent pulses, rather it collects data from a very large sample of pulses. It is safe to assume that collecting pulse information in this mode will produce jitter values somewhat larger than if consecutive cycles were measured, therefore, this measurement will represent an upper bound of cycle-to-cycle jitter. Most likely, this is a conservative estimate of the cycle-to-cycle jitter. There are two sources of jitter in a PLL based clock driver, the commonly known random jitter of the PLL and the less intuitive jitter caused by synchronous, different frequency outputs switching. For the case where all of the outputs are
TIMING SOLUTIONS BR1333 -- Rev 6
7
MOTOROLA
MPC950 MPC951
switching at the same frequency the total jitter is exactly equal to the PLL jitter. In a device, like the MPC950/951, where a number of the outputs can be switching synchronously but at different frequencies a "multi-modal" jitter distribution can be seen on the highest frequency outputs. Because the output being monitored is affected by the activity on the other outputs it is important to consider what is happening on those other outputs. From Figure 9, one can see for each rising edge on the higher frequency signal the activity on the lower frequency signal is not constant. The activity on the other outputs tends to alter the internal thresholds of the device such that the placement of the edge being monitored is displaced in time. Because the signals are synchronous the relationship is periodic and the resulting jitter is a compilation of the PLL jitter superimposed on the displaced edges. When histograms are plotted the jitter looks like a "multi-modal" distribution as pictured in Figure 9. Depending on the size of the PLL jitter and the relative displacement of the edges the "multi-modal" distribution will appear truly "multi-modal" or simply like a "fat" Gaussian distribution. Again note that in the case where all the outputs are switching at the same frequency there is no edge displacement and the jitter is reduced to that of the PLL.
1 2 1 2
Figure 10 graphically represents the PLL jitter of the MPC950/951. The data was taken for several different output configurations. By triggering on the lowest frequency output the PLL jitter can be measured for configurations in which outputs are switching at different frequencies. As one can see in the figure the PLL jitter is much less dependent on output configuration than on internal VCO frequency.
40 35 30 RMS Jitter (ps) 25 20 15 10 5 0 160 240 320 400 480 560 Conf 1 Conf 2 Conf 3
VCO Frequency (MHz) Conf 1 = All Outputs at the Same Frequency Conf 2 = 4 Outputs at X, 5 Outputs at X/2 Conf 3 = 1 Output at X, 8 Outputs at X/4
Figure 8. RMS PLL Jitter versus VCO Frequency
400 Paek-to-Peak Jitter (ps) 350 300 250 200 150 160 Conf 2 Conf 3
1
2
Peak-to-Peak PLL Jitter Peak-to-Peak Period Jitter
240
320
400
480
560
VCO Frequency (MHz) Conf 2 = 4 Outputs at X, 5 Outputs at X/2 Conf 3 = 1 Output at X, 8 Outputs at X/4
1
2
3
2
1
2
3
Figure 9. Peak-to-Peak Period Jitter versus VCO Frequency Two different configurations were chosen to look at the period displacement caused by the switching outputs. Configuration 3 is considered worst case as the "trimodal" distribution (as pictured in Figure 9) represents the largest spread between distribution peaks. Configuration 2 is considered a typical configuration with half the outputs at a high frequency and the remaining outputs at one half the high frequency. For these cases the peak-to-peak numbers are reported in Figure 11 as the sigma numbers are useless because the distributions are not Gaussian. For situations where the outputs are synchronous and switching at different frequencies the measurement technique described here is insufficient to use for establishing guaranteed limits. Other techniques are currently being investigated to identify a more accurate and repeatable measurement so that guaranteed
1
2
3
Peak-to-Peak PLL Jitter Peak-to-Peak Period Jitter
Figure 7. PLL Jitter and Edge Displacement
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TIMING SOLUTIONS BR1333 -- Rev 6
MPC950 MPC951
limits can be provided. The data generated does give a good indication of the general performance, a performance that in most cases is well within the requirements of today's microprocessors. Finally from the data there are some general guidelines that, if followed, will minimize the output jitter of the device. First and foremost always configure the device such that the VCO runs as fast as possible. This is by far the most critical parameter in minimizing jitter. Second keep the reference frequency as high as possible. More frequent updates at the phase detector will help to reduce jitter. Note that if there is a tradeoff between higher reference frequencies and higher VCO frequency always chose the higher VCO frequency to minimize jitter. The third guideline may be the most difficult, and in some cases impossible, to follow. Try to minimize the number of different frequencies sourced from a single chip. The fixed edge displacement associated with the switching noise in most cases nearly doubles the "effective" jitter of a high speed output. Power Supply Filtering The MPC950/951 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC950/951 provides separate power supplies for the output buffers (VCCO) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC950/951. Figure 10 illustrates a typical power supply filter scheme. The MPC950/951 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC950/951. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 10 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. It is recommended that the user start with an 8-10 resistor to avoid potential VCC drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed.
3.3V
RS=5-15 PLL_VCC 22F MPC950/951 VCC 0.01F 0.01F
Figure 10. Power Supply Filter Although the MPC950/951 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the On-Board Crystal Oscillator The MPC950/951 features an on-board crystal oscillator to allow for seed clock generation as well as final distribution. The on-board oscillator is completely self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC950/951 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required.
TIMING SOLUTIONS BR1333 -- Rev 6
9
MOTOROLA
MPC950 MPC951
The oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large on-board capacitors. Because the design is a series resonant design for the optimum frequency accuracy a series resonant crystal should be used (see specification table below). Unfortunately most off the shelf crystals are characterized in a parallel resonant mode. However a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel resonant mode. Therefore in the majority of cases a parallel specified crystal can be used with the MPC950/951 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. Typically a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. For most processor implementations a few hundred ppm translates into kHz inaccuracies, a level which does not represent a major issue.
fref Phase Detector LPF
VCO
/P
/N
Qn
/m
+ fVCO , fVCO + fQn * N * P m N fref + fQn *mN * P
fref m = 8 (FBsel = `1'), 16(FBsel = `0') P=1 Figure 11. PLL Block Diagram For the MPC950/951 clock driver, the following will provide an example of how to determine the crystal frequency required for a given design. Given: Qa = 160MHz Qb = 80MHz Qc = 40MHz Qd = 40MHz FBSel = `0' fref
Table 3. Crystal Specifications
Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance* 75ppm at 25C 150ppm 0 to 70C 0 to 70C 5-7pF 50 to 80 Max 100W 5ppm/Yr (First 3 Years)
+ fQn *mN * P
From Table 3 fQd = VCO/8 then N = 8 OR fQa = VCO/2 then N = 2 From Figure 11 m = 16 and P = 1 fref 8 * + 40 *16 * 1 + 20MHz OR 160 162 * 1 + 20MHz
* See accompanying text for series versus parallel resonant discussion.
The MPC950/951 is a clock driver which was designed to generate outputs with programmable frequency relationships and not a synthesizer with a fixed input frequency. As a result the crystal input frequency is a function of the desired output frequency. For a design which utilizes the external feedback to the PLL the selection of the crystal frequency is straight forward; simply chose a crystal which is equal in frequency to the fed back signal. To determine the crystal required to produce the desired output frequency for an application which utilizes internal feedback the block diagram of Figure 11 should be used. The P and the M values for the MPC950/951 are also included in Figure 11. The M values can be found in the configuration tables included in this applications section.
Driving Transmission Lines The MPC950/951 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can
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TIMING SOLUTIONS BR1333 -- Rev 6
MPC950 MPC951
be driven by each output of the MPC950/951 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 12 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC950/951 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC950/951 OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutA
towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
VOLTAGE (V)
2.0 In 1.5
1.0
0.5 MPC950/951 OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutB1 RS = 43 ZO = 50 OutB0
0 2 4 6 8 TIME (nS) 10 12 14
Figure 13. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 14 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
Figure 12. Single versus Dual Transmission Lines The waveform plots of Figure 13 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC950/951 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC950/951. The output waveform in Figure 13 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / (Rs + Ro +Zo)) Zo = 50 || 50 Rs = 43 || 43 Ro = 7 VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment
MPC950/951 OUTPUT BUFFER 7
RS = 36
ZO = 50
RS = 36
ZO = 50
7 + 36 k 36 = 50 k 50 25 = 25 Figure 14. Optimized Dual Line Termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use.
TIMING SOLUTIONS BR1333 -- Rev 6
11
MOTOROLA
MPC950 MPC951
OUTLINE DIMENSIONS
FA SUFFIX TQFP PACKAGE CASE 873A-02 ISSUE A A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
MOTOROLA
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
12
TIMING SOLUTIONS BR1333 -- Rev 6
-T-, -U-, -Z-
MPC950 MPC951
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
TIMING SOLUTIONS BR1333 -- Rev 6
13
*MPC950/D*
MPC950/D MOTOROLA

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